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| | | P | ID | Type | Category | Severity | Status | Updated | Summary |
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| | | | 0004032 | Errata | [VIP]
BCL | major | new | 2012-02-08 | Not possible to undo a factory override. |
| | |  | 0003947 | Restriction | [Power Aware P1801]
6.06 add_domain_elements | minor | editor (Qi Wang) | 2012-02-07 | What is the utility of add_domain_elements - should it be deprecated? |
| | |  | 0004006 | Clarification | [Power Aware P1801]
6.05 Error handling | minor | editor (Sree Ganesan) | 2012-02-07 | UPF Command Return Value specifications are inconsistent and not necessarily useful |
| | | | 0003986 | Clarification | [Power Aware P1801]
6.05 Error handling | minor | editor (Sree Ganesan) | 2012-02-07 | UPF Command Return Value specifications are inconsistent and not necessarily useful |
| | |  | 0003980 | Restriction | [Power Aware P1801]
6.19 create_power_domain | major | editor (Sushma Honnavara-Prasad) | 2012-02-07 | Deprecate -include_scope of create_power_domain |
| | | | 0003979 | Restriction | [Power Aware P1801]
6.19 create_power_domain | minor | editor (Sushma Honnavara-Prasad) | 2012-02-07 | Deprecate -scope of create_power_domain |
| | | | 0003957 | Errata | [Power Aware P1801]
Annex B Supply net logic type | minor | editor (Amit Srivastava) | 2012-02-07 | Change the name of Appendix B to reflect the fact that it contains Package UPF |
| | | | 0003955 | Errata | [Power Aware P1801]
Annex B Supply net logic type | minor | editor (Amit Srivastava) | 2012-02-07 | Correct VHDL package UPF to avoid use of reserved word as a parameter name |
| | | | 0003945 | Errata | [Power Aware P1801]
Annex C Value conversion tables (VCTs) | minor | editor (Amit Srivastava) | 2012-02-07 | Predefined VCTs of hdl_type SV have an additional ' in the definition this is not consistent with the syntax |
| | | | 0003910 | Clarification | [Power Aware P1801]
6.37 set_design_attributes | minor | editor (Amit Srivastava) | 2012-02-07 | Correct syntax of set_design_attributes to be consistent with tcl syntax |
| | | | 0003868 | Clarification | [Power Aware P1801]
6.40 set_isolation | minor | editor (Shir-Shen Chang) | 2012-02-07 | AKA 3194c: Shall we define 'sibling' in Definitions? |
| | | | 0003867 | Clarification | [Power Aware P1801]
6.40 set_isolation | minor | editor (Shir-Shen Chang) | 2012-02-07 | AKA 3194b: Clarification on '-location sibling' where tools should create one hierarchy per strategy, per domain or per port? |
| | | | 0003864 | Clarification | [Power Aware P1801]
6.40 set_isolation | text | editor (Erich Marschner) | 2012-02-07 | AKA 2799b: Clarify the semantics of -source/-sink, relates to the difference between driving logic vs driving design elements |
| | | | 0003793 | Errata | [Power Aware P1801]
6.40 set_isolation | minor | editor (Sushma Honnavara-Prasad) | 2012-02-07 | Remove -transitive=TRUE (currently the default) in set_isolation and set_level_shifter |
| | | | 0004031 | Errata | [VIP]
BCL | major | new | 2012-02-07 | uvm_pack_* macros ignore endianness |
| | | | 0004030 | Errata | [VIP]
BCL | minor | new | 2012-02-07 | `uvm_*pack_* macros lack begin/end |
| | | | 0003707 | Clarification | [Power Aware P1801]
6.45 set_port_attributes | major | editor (David Cheng) | 2012-02-07 | Clarify how the default driver/receiver supplies of primary inputs/ouputs are determined |
| | | | 0003415 | Errata | [Power Aware P1801]
6.08 add_power_state | minor | editor (Joe Daniels) | 2012-02-07 | Check the example and decide whether SLEEP_MODE should involve reverse bias rather than forward bias - fix |
| | | | 0003320 | Clarification | [Power Aware P1801]
6.40 set_isolation | minor | editor (Shir-Shen Chang) | 2012-02-07 | Clarification on the instantiation hierarchy for '-location sibling' in set_isolation/level_shifter, see also 3194 |
| | | | 0003194 | Clarification | [Power Aware P1801]
6.40 set_isolation | minor | editor (Shir-Shen Chang) | 2012-02-07 | AKA 3194a: Clarification on the term 'sibling' when used to define location. (see 3320 for #1) |
| | | | 0003043 | Clarification | [Power Aware P1801]
3.01 Definitions | minor | editor (Erich Marschner) | 2012-02-07 | Review and revise Clause 3 Definitions as required. |
| | | | 0003042 | Clarification | [Power Aware P1801]
3.01 Definitions | minor | editor (Erich Marschner) | 2012-02-07 | Clarify whether Verilog primitives create drivers |
| | | | 0003040 | Errata | [Power Aware P1801]
6.08 add_power_state | major | editor (Amit Srivastava) | 2012-02-07 | Revise add_power_state syntax to conform to UPF conventions |
| | | | 0002966 | Clarification | [Power Aware P1801]
6.01 Conventions used | minor | editor (Amit Srivastava) | 2012-02-07 | Check that use of {} is self-consistent and consistent with tcl and revise as needed. |
| | | | 0002965 | Clarification | [Power Aware P1801]
6.08 add_power_state | feature | editor (Amit Srivastava) | 2012-02-07 | Clarify that add_power_state requires an empty set of braces in certain cases (cf 3040) |
| | | | 0002868 | Clarification | [Power Aware P1801]
7.01 find_objects | minor | editor (Erich Marschner) | 2012-02-07 | FAQ: Clarify whether -transitive is allowed with no value |
| | | | 0002857 | Clarification | [Power Aware P1801]
7.01 find_objects | major | editor (Joe Daniels) | 2012-02-07 | AKA 2857a: Clarify meaning of -transitive FALSE, -transitive TRUE on find_objects |
| | | | 0002849 | Clarification | [Power Aware P1801]
4.03.1 Explicit connection of supply nets | major | editor (Joe Daniels) | 2012-02-07 | Clarify that whenever a supply net ref is required, the supply net handle can be used |
| | | | 0002604 | Clarification | [Power Aware P1801]
6.46 set_power_switch | minor | editor (Amit Srivastava) | 2012-02-07 | AKA 2604a: Request to add scope to set_power_switch |
| | | | 0003884 | Enhancement | [SystemVerilog P1800]
SV-CC | feature | completed (Stuart Sutherland) | 2012-02-06 | VPI support for soft constraints |
| | |  | 0003599 | Errata | [SystemVerilog P1800]
SV-CC | text | completed (Jim Vellenga) | 2012-02-06 | svBitVecVal as reference type is missing asterisk |
| | | | 0003589 | Errata | [SystemVerilog P1800]
SV-EC | minor | completed (Stuart Sutherland) | 2012-02-06 | Place holder for all editorial issues for SV-EC sub-committee |
| | | | 0003938 | Clarification | [Power Aware P1801]
5.04.2 Power states of supply sets | minor | review (Amit Srivastava) | 2012-02-06 | Clarify interaction of -update refinement with refinement of NOT_NORMAL, and define a default simstate |
| | | | 0003295 | Enhancement | [SystemVerilog P1800]
SV-AC | feature | completed (Manisha Kulshrestha) | 2012-02-06 | need a way to control only asserts/covers/assume directives |
| | | | 0003293 | Clarification | [SystemVerilog P1800]
SV-EC | minor | completed (Arturo Salz) | 2012-02-06 | Clarify $cast behaviour on class handles |
| | | | 0003278 | Errata | [SystemVerilog P1800]
SV-EC | major | completed (Françoise Martinolle) | 2012-02-06 | virtual method type rules |
| | | | 0003213 | Errata | [SystemVerilog P1800]
SV-AC | minor | completed (Dmitry Korchemny) | 2012-02-06 | Update definition of sampled value |
| | | | 0003985 | Errata | [VIP]
Registers | major | resolved (Janick Bergeron) | 2012-02-06 | get_mem_by_offset doesn't work |
| | | | 0003472 | Enhancement | [VIP]
Resources | minor | resolved (Janick Bergeron) | 2012-02-06 | deprecate set_config/get_config interface for configuration |
| | | | 0003206 | Enhancement | [SystemVerilog P1800]
SV-AC | major | completed (Erik_Seligman) | 2012-02-06 | Deferred assertions are sensitive to glitches |
| | | | 0003192 | Errata | [SystemVerilog P1800]
SV-CC | minor | completed (Chuck_Berking) | 2012-02-06 | 37.8 section has wrong value definitions for vpiAccessType |
| | | | 0003113 | Errata | [SystemVerilog P1800]
SV-AC | minor | completed (Laurence Bisht) | 2012-02-06 | Add port_identifier to constant_primary BNF for sequences, properties and checkers |
| | | | 0003033 | Enhancement | [SystemVerilog P1800]
SV-AC | feature | completed (Dmitry Korchemny) | 2012-02-06 | Enhance checker modeling capabilities |
| | | | 0002987 | Enhancement | [SystemVerilog P1800]
SV-EC | feature | completed (Arturo Salz) | 2012-02-06 | Soft Constraints |
| | | | 0002949 | Errata | [SystemVerilog P1800]
SV-EC | minor | completed (Jonathan Bromley) | 2012-02-06 | LRM is silent about the semantics of referencing a clocking block output |
| | | | 0002506 | Enhancement | [SystemVerilog P1800]
SV-EC | feature | completed (Scott Little) | 2012-02-06 | Non-trivial coverage space shapes and joint conditions are difficult to specify with covergroups |
| | | | 0002093 | Enhancement | [SystemVerilog P1800]
SV-AC | feature | completed (Dmitry Korchemny) | 2012-02-06 | Checker construct should permit output arguments |
| | | | 0001523 | Errata | [SystemVerilog P1800]
SV-BC | major | completed (Shalom Bresticker) | 2012-02-06 | How is ?: defined for non-integral data types? |
| | | | 0001356 | Enhancement | [SystemVerilog P1800]
SV-EC | feature | completed (Thomas R Alsop) | 2012-02-06 | Multiple inheritance |
| | | | 0003122 | Clarification | [Power Aware P1801]
6.19 create_power_domain | minor | resolved (David Cheng) | 2012-02-06 | Clarify create_power_domain semantics when none of -include_scope, -elements, -update are specified |
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