Unassigned [^] (1 - 10 / 980) 0004031   uvm_pack_* macros ignore endianness [VIP] BCL - 2012-02-07 12:14 0004030   `uvm_*pack_* macros lack begin/end [VIP] BCL - 2012-02-07 12:13 0002390   Can aggregation be used in a dynamic array "new" initializer? [SystemVerilog P1800] SV-EC - 2012-02-01 15:21 0003394   invalid example for dynamic array [SystemVerilog P1800] SV-EC - 2012-02-01 14:46 0003268   issue with flushing the fifo when there are waiting put processes [VIP] BCL - 2012-02-01 08:28 0003454   Enhance uvm_barrier API to include explicit registration [VIP] BCL - 2012-02-01 08:28 0003419   uvm_sequence_base::starting_phase not set for manually started sequences [VIP] Phasing - 2012-02-01 08:28 0003662   packing of strings using NULL termination not compatible with bitstream ops [VIP] BCL - 2012-02-01 08:26 0003655   policy classes (packet/printer, comparer) need to extend uvm_object, invoke `uvm_object_utils [VIP] BCL - 2012-02-01 08:26 0003652 Add event parameter to finish_item, `uvm_do macros [VIP] BCL - 2012-02-01 08:25	Resolved [^] (1 - 10 / 51) 0003884   VPI support for soft constraints [SystemVerilog P1800] SV-CC - 2012-02-06 16:38 0003599 svBitVecVal as reference type is missing asterisk [SystemVerilog P1800] SV-CC - 2012-02-06 16:36 0003589   Place holder for all editorial issues for SV-EC sub-committee [SystemVerilog P1800] SV-EC - 2012-02-06 16:26 0003295   need a way to control only asserts/covers/assume directives [SystemVerilog P1800] SV-AC - 2012-02-06 16:22 0003293   Clarify $cast behaviour on class handles [SystemVerilog P1800] SV-EC - 2012-02-06 13:38 0003278   virtual method type rules [SystemVerilog P1800] SV-EC - 2012-02-06 13:35 0003213   Update definition of sampled value [SystemVerilog P1800] SV-AC - 2012-02-06 13:31 0003206   Deferred assertions are sensitive to glitches [SystemVerilog P1800] SV-AC - 2012-02-06 11:53 0003192   37.8 section has wrong value definitions for vpiAccessType [SystemVerilog P1800] SV-CC - 2012-02-06 11:47 0003113   Add port_identifier to constant_primary BNF for sequences, properties and checkers [SystemVerilog P1800] SV-AC - 2012-02-06 11:44
Recently Modified [^] (1 - 10 / 3978) 0003947 What is the utility of add_domain_elements - should it be deprecated? [Power Aware P1801] 6.06 add_domain_elements - 2012-02-07 12:20 0004006 UPF Command Return Value specifications are inconsistent and not necessarily useful [Power Aware P1801] 6.05 Error handling - 2012-02-07 12:17 0003986 UPF Command Return Value specifications are inconsistent and not necessarily useful [Power Aware P1801] 6.05 Error handling - 2012-02-07 12:17 0003980 Deprecate -include_scope of create_power_domain [Power Aware P1801] 6.19 create_power_domain - 2012-02-07 12:17 0003979 Deprecate -scope of create_power_domain [Power Aware P1801] 6.19 create_power_domain - 2012-02-07 12:17 0003957 Change the name of Appendix B to reflect the fact that it contains Package UPF [Power Aware P1801] Annex B Supply net logic type - 2012-02-07 12:17 0003955 Correct VHDL package UPF to avoid use of reserved word as a parameter name [Power Aware P1801] Annex B Supply net logic type - 2012-02-07 12:17 0003945 Predefined VCTs of hdl_type SV have an additional ' in the definition this is not consistent with the syntax [Power Aware P1801] Annex C Value conversion tables (VCTs) - 2012-02-07 12:17 0003910 Correct syntax of set_design_attributes to be consistent with tcl syntax [Power Aware P1801] 6.37 set_design_attributes - 2012-02-07 12:17 0003868 AKA 3194c: Shall we define 'sibling' in Definitions? [Power Aware P1801] 6.40 set_isolation - 2012-02-07 12:17
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