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<description>EDA.org Mantis - ISSUES</description>
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<title>EDA.org Mantis - ISSUES</title>
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<title>EDA.org Mantis - ISSUES</title>
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<link>http://www.verilog.org/svdb/</link>
<description>EDA.org Mantis - ISSUES</description>
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<sy:updateBase>2012-02-08T04:26:09-08:00</sy:updateBase>
<item>
<title>0003947: What is the utility of add_domain_elements - should it be deprecated?</title>
<link>http://www.verilog.org/svdb/view.php?id=3947</link>
<description>Under section 6.6 add_domain_elements on page 43 the LRM says:&lt;br /&gt;
&lt;br /&gt;
This command is semantically equivalent to&lt;br /&gt;
&lt;br /&gt;
   proc add_domain_elements {dn elements el} {&lt;br /&gt;
      if { string equal $elements &quot;-elements&quot; }{&lt;br /&gt;
         create_power_domain $dn -update -elements $el&lt;br /&gt;
         return 1&lt;br /&gt;
      } else {&lt;br /&gt;
         return -code TCL_ERROR \&lt;br /&gt;
            -errorcode $ecode \&lt;br /&gt;
            -errorinfo $einfo \&lt;br /&gt;
            $resulttext&lt;br /&gt;
      }&lt;br /&gt;
   }&lt;br /&gt;
&lt;br /&gt;
I guess &quot;add_domain_elements&quot; is more intuitive than &quot;create_power_domain -update&quot; (which seems a little contradictory) - but to we need to support and maintain two ways to do the same thing?&lt;br /&gt;
&lt;br /&gt;
Should add_domain_elements  be deprecated?</description>
<guid>http://www.verilog.org/svdb/view.php?id=3947</guid>
<author>John Biggs &lt;John Biggs@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3947#bugnotes</comments>
</item>
<item>
<title>0004006: UPF Command Return Value specifications are inconsistent and not necessarily useful</title>
<link>http://www.verilog.org/svdb/view.php?id=4006</link>
<description>The return value specification for UPF commands is not as consistent as it could be, and probably should be.  Following is a list of the Return value specifications (from the syntax table in each case) for every UPF command.  Those that have the same definition are grouped under one copy of the definition.&lt;br /&gt;
&lt;br /&gt;
Most commands return a 1 if successful.  Some commands - in particular, those that define objects - return the name of the created object.  However, this is not consistent; for example, commands to create a supply port, supply net, or logic port return the name of the created object, but create_logic_net does not.&lt;br /&gt;
&lt;br /&gt;
For those that return names, the specification usually says &quot;the fully qualified name&quot;, but for create_pst, it just refers to &quot;the name&quot;.&lt;br /&gt;
&lt;br /&gt;
For those that return names, the specification typically qualifies this with &quot;(from the active scope)&quot;, but for create_supply_net, the qualification is &quot;(from the scope in which the net is created)&quot;, and for find_objects, the qualification is &quot;(relative to the active scope)&quot;.  The variation in wording seems to imply subtle differences in meaning, but it is not clear what those differences are.&lt;br /&gt;
&lt;br /&gt;
It would be good to streamline these definitions a bit, especially in light of the UPF Processing steps.  Given that UPF command processing necessarily involves constructing an internal representation of the commands so UPF semantic analysis can be done before they are executed (to construct the power intent model), there seems to be little value in any command except those that only have immediate execution semantics (see UPF Processing) to return any values.&lt;br /&gt;
&lt;br /&gt;
Following is the detailed summary of return values:&lt;br /&gt;
&lt;br /&gt;
Return a 1 if successful or raise a TCL_ERROR if not&lt;br /&gt;
add_domain_elements&lt;br /&gt;
add_power_state&lt;br /&gt;
add_pst_state&lt;br /&gt;
associate_supply_set&lt;br /&gt;
bind_checker&lt;br /&gt;
connect_logic_net&lt;br /&gt;
connect_supply_set&lt;br /&gt;
create_composite_domain&lt;br /&gt;
create_hdl2upf_vct&lt;br /&gt;
create_logic_net&lt;br /&gt;
create_supply_set&lt;br /&gt;
create_upf2hdl_vct&lt;br /&gt;
describe_state_transition&lt;br /&gt;
load_simstate_behavior&lt;br /&gt;
map_isolation_cell&lt;br /&gt;
map_level_shifter_cell&lt;br /&gt;
map_power_switch&lt;br /&gt;
map_retention_cell&lt;br /&gt;
name_format&lt;br /&gt;
save_upf&lt;br /&gt;
set_design_attributes&lt;br /&gt;
set_design_top&lt;br /&gt;
set_domain_supply_net&lt;br /&gt;
set_isolation&lt;br /&gt;
set_isolation_control&lt;br /&gt;
set_level_shifter&lt;br /&gt;
set_pin_related_supply&lt;br /&gt;
set_port_attributes&lt;br /&gt;
set_power_switch&lt;br /&gt;
set_retention&lt;br /&gt;
set_retention_control&lt;br /&gt;
set_retention_elements&lt;br /&gt;
set_simstate_behavior&lt;br /&gt;
use_interface_cell&lt;br /&gt;
&lt;br /&gt;
Return a list of the found hierarchical names (relative to the active scope); when nothing is found, a null string is returned.&lt;br /&gt;
find_objects&lt;br /&gt;
&lt;br /&gt;
If called with an argument, return the argument.  If called with no arguments, return the current version number.  If the call fails, raise a TCL_ERROR.&lt;br /&gt;
upf_version&lt;br /&gt;
&lt;br /&gt;
Return the number of power domains merged or raise a TCL_ERROR if the merge is unsuccessful.&lt;br /&gt;
merge_power_domains&lt;br /&gt;
&lt;br /&gt;
Return a 1 if all commands in the loaded UPF file completed successfully, or raise a TCL_ERROR if the command fails or any command in the loaded UPF file fails.&lt;br /&gt;
load_upf&lt;br /&gt;
load_upf_protected&lt;br /&gt;
&lt;br /&gt;
Return the name of the created PST or raise a TCL_ERROR if the PST is not created.&lt;br /&gt;
create_pst&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name of the created switch or raise a TCL_ERROR if the domain is not created.&lt;br /&gt;
create_power_switch	&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the active scope) of the created domain or raise a TCL_ERROR if the switch is not created.&lt;br /&gt;
create_power domain	&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the active scope) of the created port or raise a TCL_ERROR if the port is not created.&lt;br /&gt;
create_logic_port	&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the active scope) of the created port or raise a TCL_ERROR if any of the port states are not added.&lt;br /&gt;
add_port_state&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the scope in which the net is created) of the created net or raise a TCL_ERROR if the net is not created.&lt;br /&gt;
create_supply_net&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the active scope) of the created port or raise a TCL_ERROR if the port is not created.&lt;br /&gt;
create_supply_port&lt;br /&gt;
&lt;br /&gt;
Return the active scope prior to execution of the command as a full path string relative to the active design top if successful or raise a TCL_ERROR if it fails (e.g., if the instance does not exist.)&lt;br /&gt;
set_scope&lt;br /&gt;
&lt;br /&gt;
Return the setting of the translation if successful or raise a TCL_ERROR if not.&lt;br /&gt;
set_partial_on_translation&lt;br /&gt;
&lt;br /&gt;
If TCL_ERROR is raised, then errorcode, errorinfo, and resulttext are also available.</description>
<guid>http://www.verilog.org/svdb/view.php?id=4006</guid>
<author>Colin Holehouse &lt;Colin Holehouse@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=4006#bugnotes</comments>
</item>
<item>
<title>0003986: UPF Command Return Value specifications are inconsistent and not necessarily useful</title>
<link>http://www.verilog.org/svdb/view.php?id=3986</link>
<description>The return value specification for UPF commands is not as consistent as it could be, and probably should be.  Following is a list of the Return value specifications (from the syntax table in each case) for every UPF command.  Those that have the same definition are grouped under one copy of the definition.&lt;br /&gt;
&lt;br /&gt;
Most commands return a 1 if successful.  Some commands - in particular, those that define objects - return the name of the created object.  However, this is not consistent; for example, commands to create a supply port, supply net, or logic port return the name of the created object, but create_logic_net does not.&lt;br /&gt;
&lt;br /&gt;
For those that return names, the specification usually says &quot;the fully qualified name&quot;, but for create_pst, it just refers to &quot;the name&quot;.&lt;br /&gt;
&lt;br /&gt;
For those that return names, the specification typically qualifies this with &quot;(from the active scope)&quot;, but for create_supply_net, the qualification is &quot;(from the scope in which the net is created)&quot;, and for find_objects, the qualification is &quot;(relative to the active scope)&quot;.  The variation in wording seems to imply subtle differences in meaning, but it is not clear what those differences are.&lt;br /&gt;
&lt;br /&gt;
It would be good to streamline these definitions a bit, especially in light of the UPF Processing steps.  Given that UPF command processing necessarily involves constructing an internal representation of the commands so UPF semantic analysis can be done before they are executed (to construct the power intent model), there seems to be little value in any command except those that only have immediate execution semantics (see UPF Processing) to return any values.&lt;br /&gt;
&lt;br /&gt;
Following is the detailed summary of return values:&lt;br /&gt;
&lt;br /&gt;
Return a 1 if successful or raise a TCL_ERROR if not&lt;br /&gt;
add_domain_elements&lt;br /&gt;
add_power_state&lt;br /&gt;
add_pst_state&lt;br /&gt;
associate_supply_set&lt;br /&gt;
bind_checker&lt;br /&gt;
connect_logic_net&lt;br /&gt;
connect_supply_set&lt;br /&gt;
create_composite_domain&lt;br /&gt;
create_hdl2upf_vct&lt;br /&gt;
create_logic_net&lt;br /&gt;
create_supply_set&lt;br /&gt;
create_upf2hdl_vct&lt;br /&gt;
describe_state_transition&lt;br /&gt;
load_simstate_behavior&lt;br /&gt;
map_isolation_cell&lt;br /&gt;
map_level_shifter_cell&lt;br /&gt;
map_power_switch&lt;br /&gt;
map_retention_cell&lt;br /&gt;
name_format&lt;br /&gt;
save_upf&lt;br /&gt;
set_design_attributes&lt;br /&gt;
set_design_top&lt;br /&gt;
set_domain_supply_net&lt;br /&gt;
set_isolation&lt;br /&gt;
set_isolation_control&lt;br /&gt;
set_level_shifter&lt;br /&gt;
set_pin_related_supply&lt;br /&gt;
set_port_attributes&lt;br /&gt;
set_power_switch&lt;br /&gt;
set_retention&lt;br /&gt;
set_retention_control&lt;br /&gt;
set_retention_elements&lt;br /&gt;
set_simstate_behavior&lt;br /&gt;
use_interface_cell&lt;br /&gt;
&lt;br /&gt;
Return a list of the found hierarchical names (relative to the active scope); when nothing is found, a null string is returned.&lt;br /&gt;
find_objects&lt;br /&gt;
&lt;br /&gt;
If called with an argument, return the argument.  If called with no arguments, return the current version number.  If the call fails, raise a TCL_ERROR.&lt;br /&gt;
upf_version&lt;br /&gt;
&lt;br /&gt;
Return the number of power domains merged or raise a TCL_ERROR if the merge is unsuccessful.&lt;br /&gt;
merge_power_domains&lt;br /&gt;
&lt;br /&gt;
Return a 1 if all commands in the loaded UPF file completed successfully, or raise a TCL_ERROR if the command fails or any command in the loaded UPF file fails.&lt;br /&gt;
load_upf&lt;br /&gt;
load_upf_protected&lt;br /&gt;
&lt;br /&gt;
Return the name of the created PST or raise a TCL_ERROR if the PST is not created.&lt;br /&gt;
create_pst&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name of the created switch or raise a TCL_ERROR if the domain is not created.&lt;br /&gt;
create_power_switch	&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the active scope) of the created domain or raise a TCL_ERROR if the switch is not created.&lt;br /&gt;
create_power domain	&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the active scope) of the created port or raise a TCL_ERROR if the port is not created.&lt;br /&gt;
create_logic_port	&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the active scope) of the created port or raise a TCL_ERROR if any of the port states are not added.&lt;br /&gt;
add_port_state&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the scope in which the net is created) of the created net or raise a TCL_ERROR if the net is not created.&lt;br /&gt;
create_supply_net&lt;br /&gt;
&lt;br /&gt;
Return the fully qualified name (from the active scope) of the created port or raise a TCL_ERROR if the port is not created.&lt;br /&gt;
create_supply_port&lt;br /&gt;
&lt;br /&gt;
Return the active scope prior to execution of the command as a full path string relative to the active design top if successful or raise a TCL_ERROR if it fails (e.g., if the instance does not exist.)&lt;br /&gt;
set_scope&lt;br /&gt;
&lt;br /&gt;
Return the setting of the translation if successful or raise a TCL_ERROR if not.&lt;br /&gt;
set_partial_on_translation&lt;br /&gt;
&lt;br /&gt;
If TCL_ERROR is raised, then errorcode, errorinfo, and resulttext are also available.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3986</guid>
<author>Erich Marschner &lt;Erich Marschner@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3986#bugnotes</comments>
</item>
<item>
<title>0003980: Deprecate -include_scope of create_power_domain</title>
<link>http://www.verilog.org/svdb/view.php?id=3980</link>
<description>Per WG discussion on Dec. 9 2011, the resolution is to deprecate -include_scope.&lt;br /&gt;
Related mantis is 3122. Also, see discussion notes covering this topic in:&lt;br /&gt;
&lt;a href=&quot;https://docs.google.com/a/p1801.org/?tab=oo&amp;pli=1#advanced-search/q=3775&quot;&gt;https://docs.google.com/a/p1801.org/?tab=oo&amp;pli=1#advanced-search/q=3775&lt;/a&gt; [&lt;a href=&quot;https://docs.google.com/a/p1801.org/?tab=oo&amp;pli=1#advanced-search/q=3775&quot; target=&quot;_blank&quot;&gt;^&lt;/a&gt;]</description>
<guid>http://www.verilog.org/svdb/view.php?id=3980</guid>
<author>Qi Wang &lt;Qi Wang@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3980#bugnotes</comments>
</item>
<item>
<title>0003979: Deprecate -scope of create_power_domain</title>
<link>http://www.verilog.org/svdb/view.php?id=3979</link>
<description>Per WG discussion on Dec. 9 2011, the resolution is to deprecate -scope.&lt;br /&gt;
See google docs: &lt;a href=&quot;https://docs.google.com/a/p1801.org/?tab=oo&amp;pli=1#advanced-search/q=3775&quot;&gt;https://docs.google.com/a/p1801.org/?tab=oo&amp;pli=1#advanced-search/q=3775&lt;/a&gt; [&lt;a href=&quot;https://docs.google.com/a/p1801.org/?tab=oo&amp;pli=1#advanced-search/q=3775&quot; target=&quot;_blank&quot;&gt;^&lt;/a&gt;]&lt;br /&gt;
&lt;br /&gt;
The related mantis is 3775</description>
<guid>http://www.verilog.org/svdb/view.php?id=3979</guid>
<author>Qi Wang &lt;Qi Wang@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3979#bugnotes</comments>
</item>
<item>
<title>0003957: Change the name of Appendix B to reflect the fact that it contains Package UPF</title>
<link>http://www.verilog.org/svdb/view.php?id=3957</link>
<description>The entry for Appendix B in the Category field above is mislabeled as &quot;Supply net logic type&quot;, which seems strange given that 99% of the appendix is about package UPF.  This apparently came about because Appendix B starts with a short paragraph about representing supply net type values before presenting B.1 VHDL and B.2 SystemVerilog, both of which contain respective versions of the package.  The title of the appendix appears to have come from that short paragraph.  It would be better if this appendix were entitled Package UPF, with the section on supply net logic type as B.1, the VHDL UPF package as B.2, and the SystemVerilog UPF package as B.3.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3957</guid>
<author>Erich Marschner &lt;Erich Marschner@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3957#bugnotes</comments>
</item>
<item>
<title>0003955: Correct VHDL package UPF to avoid use of reserved word as a parameter name</title>
<link>http://www.verilog.org/svdb/view.php?id=3955</link>
<description>Package UPF contains function assign_supply_state, which has a parameter named &quot;after&quot;.  This is a VHDL reserved word.  Reserved words can only be used as keywords, not as user-defined (or predefined) identifiers, so the package won't (or at least shouldn't) compile as is.  This parameter name should be changed to something else, such as &quot;delay&quot;.&lt;br /&gt;
&lt;br /&gt;
The same function exists in both VHDL and Verilog UPF packages.  Ideally both would use the same non-reserved identifier.&lt;br /&gt;
&lt;br /&gt;
I've marked this as an Errata, which is the closest thing to Bug that is available in the category list.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3955</guid>
<author>Erich Marschner &lt;Erich Marschner@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3955#bugnotes</comments>
</item>
<item>
<title>0003945: Predefined VCTs of hdl_type SV have an additional ' in the definition this is not consistent with the syntax</title>
<link>http://www.verilog.org/svdb/view.php?id=3945</link>
<description>The predefined VCTs which provide conversion to/from SV logic type have and addition ' character in before (and after in some cases ) the logic values. This is not consistent with the syntax defined create_hdl2upf_vct and create_upf2hdl_vct commands. e.g.&lt;br /&gt;
&lt;br /&gt;
C.6 UPF2SV_LOGIC&lt;br /&gt;
create_upf2hdl_vct UPF2SV_LOGIC&lt;br /&gt;
-hdl_type sv&lt;br /&gt;
-table {{UNDETERMINED 'X}&lt;br /&gt;
{PARTIAL_ON 'X}&lt;br /&gt;
{FULL_ON '1}&lt;br /&gt;
{OFF '0}}&lt;br /&gt;
&lt;br /&gt;
----&lt;br /&gt;
This should be &lt;br /&gt;
&lt;br /&gt;
C.6 UPF2SV_LOGIC&lt;br /&gt;
create_upf2hdl_vct UPF2SV_LOGIC&lt;br /&gt;
-hdl_type sv&lt;br /&gt;
-table {{UNDETERMINED X}&lt;br /&gt;
{PARTIAL_ON X}&lt;br /&gt;
{FULL_ON 1}&lt;br /&gt;
{OFF 0}}&lt;br /&gt;
&lt;br /&gt;
as per following statement on page 70 and example on page 71.&lt;br /&gt;
When converting to SystemVerilog logic type, the set of legal values is 0, 1, X, and Z.&lt;br /&gt;
&lt;br /&gt;
Syntax examples:&lt;br /&gt;
create_upf2hdl_vct upf2vlog_vdd&lt;br /&gt;
-hdl_type {sv}&lt;br /&gt;
-table {{OFF X} {FULL_ON 1} {PARTIAL_ON 0}}&lt;br /&gt;
&lt;br /&gt;
The affected vcts are&lt;br /&gt;
C.5 SV_LOGIC2UPF&lt;br /&gt;
C.6 UPF2SV_LOGIC&lt;br /&gt;
C.7 SV_LOGIC2UPF_GNDZERO&lt;br /&gt;
C.8 UPF_GNDZERO2SV_LOGIC&lt;br /&gt;
C.10 SV_TIED_HI&lt;br /&gt;
C.12 SV_TIED_LO</description>
<guid>http://www.verilog.org/svdb/view.php?id=3945</guid>
<author>Amit Srivastava &lt;Amit Srivastava@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3945#bugnotes</comments>
</item>
<item>
<title>0003910: Correct syntax of set_design_attributes to be consistent with tcl syntax</title>
<link>http://www.verilog.org/svdb/view.php?id=3910</link>
<description>In 1801-2009 UPF, the syntax for set_design_attributes includes the option&lt;br /&gt;
&lt;br /&gt;
  -attribute name value&lt;br /&gt;
&lt;br /&gt;
which can appear multiple times.&lt;br /&gt;
&lt;br /&gt;
According to &lt;a href=&quot;http://www.verilog.org/svdb/view.php?id=3040&quot;&gt;0003040&lt;/a&gt;, which talks about the consistency of add_power_state with tcl syntax, &lt;br /&gt;
&lt;br /&gt;
  &quot;According to section 6.1, All parameters begin with a hyphen (-)....&quot;. So -state defines a parameter. According to Tcl syntax, a parameter has three basic data types:&lt;br /&gt;
&lt;br /&gt;
a.	Scalar (or string)&lt;br /&gt;
b.	List (an ordered list of scalars)&lt;br /&gt;
c.	Array (or hash)&quot;&lt;br /&gt;
&lt;br /&gt;
This implies that the syntax for the -attribute option of set_design_attributes should be &lt;br /&gt;
&lt;br /&gt;
  -attribute { name value }&lt;br /&gt;
&lt;br /&gt;
since the 'value' of this parameter consists of a list of two items, not a single item or a general array/hash.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3910</guid>
<author>Erich Marschner &lt;Erich Marschner@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3910#bugnotes</comments>
</item>
<item>
<title>0003868: AKA 3194c: Shall we define 'sibling' in Definitions?</title>
<link>http://www.verilog.org/svdb/view.php?id=3868</link>
<description>Whilst the other values of 'location' define where in the hierarchy (domain or logical?) the cells should be inserted the value 'sibling' does not seem to.&lt;br /&gt;
&lt;br /&gt;
&quot;sibling—a new sibling is created into which the isolation cells are placed.&quot;&lt;br /&gt;
&lt;br /&gt;
1. This infers that new hierarchy is created to store the cells of this strategy but where should this reside? Should we assume the location for this new hierarchy is derived from automatic location or something else?&lt;br /&gt;
&lt;br /&gt;
2. This probably depends on the answer to #1 but is one sibling used per strategy or per domain?&lt;br /&gt;
&lt;br /&gt;
3. Should 'sibling' be entered in 3.1 Definitions?&lt;br /&gt;
&lt;br /&gt;
Location sibling is also used in 6.41 and 6.42.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3868</guid>
<author>Joe Daniels &lt;Joe Daniels@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3868#bugnotes</comments>
</item>
<item>
<title>0003867: AKA 3194b: Clarification on '-location sibling' where tools should create one hierarchy per strategy, per domain or per port?</title>
<link>http://www.verilog.org/svdb/view.php?id=3867</link>
<description>Whilst the other values of 'location' define where in the hierarchy (domain or logical?) the cells should be inserted the value 'sibling' does not seem to.&lt;br /&gt;
&lt;br /&gt;
&quot;sibling—a new sibling is created into which the isolation cells are placed.&quot;&lt;br /&gt;
&lt;br /&gt;
1. This infers that new hierarchy is created to store the cells of this strategy but where should this reside? Should we assume the location for this new hierarchy is derived from automatic location or something else?&lt;br /&gt;
&lt;br /&gt;
2. This probably depends on the answer to #1 but is one sibling used per strategy or per domain?&lt;br /&gt;
&lt;br /&gt;
3. Should 'sibling' be entered in 3.1 Definitions?&lt;br /&gt;
&lt;br /&gt;
Location sibling is also used in 6.41 and 6.42.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3867</guid>
<author>Joe Daniels &lt;Joe Daniels@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3867#bugnotes</comments>
</item>
<item>
<title>0003864: AKA 2799b: Clarify the semantics of -source/-sink, relates to the difference between driving logic vs driving design elements</title>
<link>http://www.verilog.org/svdb/view.php?id=3864</link>
<description>module A (out1);&lt;br /&gt;
output out1;&lt;br /&gt;
endmodule&lt;br /&gt;
module B (in1);&lt;br /&gt;
input in1;&lt;br /&gt;
endmodule&lt;br /&gt;
module TOP();&lt;br /&gt;
A instA(.out1(across));&lt;br /&gt;
B instB(.in1(across));&lt;br /&gt;
endmodule&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
set_scope&lt;br /&gt;
create_power_domain PD_yellow –include_scope&lt;br /&gt;
create_power_domain PD_red –elements instA&lt;br /&gt;
create_power_domain PD_blue –elements instB&lt;br /&gt;
set_isolation iso1 –domain PD_red –source PD_red –sink PD_blue&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
Question – does the net ‘across’ exist in domain PD_yellow&lt;br /&gt;
i.e. does the net go from PD_red to PD_yellow and then from PD_yellow to PD_blue, or does it go directly from PD_red to PD_blue?&lt;br /&gt;
So does the isolation rule select instA/out1 as being a source and instB/in1 as being a sink?</description>
<guid>http://www.verilog.org/svdb/view.php?id=3864</guid>
<author>Joe Daniels &lt;Joe Daniels@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3864#bugnotes</comments>
</item>
<item>
<title>0003793: Remove -transitive=TRUE (currently the default) in set_isolation and set_level_shifter</title>
<link>http://www.verilog.org/svdb/view.php?id=3793</link>
<description>The description of the -transitive option in set_isolation and set_level_shifter says:&lt;br /&gt;
&lt;br /&gt;
&quot;When -transitive is TRUE (the default), the command applies to the&lt;br /&gt;
descendants of the elements.&quot;&lt;br /&gt;
&lt;br /&gt;
The problem is, isolation and level_shifter cells are always inserted at domain interface. This implies that the strategy never applies to the decendants anyways, i.e., -transitive being TRUE or FALSE makes no difference.&lt;br /&gt;
&lt;br /&gt;
In contrast, -transitive in set_retention has its meaning.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3793</guid>
<author>David Cheng &lt;David Cheng@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3793#bugnotes</comments>
</item>
<item>
<title>0004031: uvm_pack_* macros ignore endianness</title>
<link>http://www.verilog.org/svdb/view.php?id=4031</link>
<description>The macros don't consider the big_endian field like the functions they replace.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
`define uvm_pack_intN(VAR,SIZE) \&lt;br /&gt;
   packer.m_bits[packer.count +: SIZE] = VAR; \&lt;br /&gt;
   packer.count += SIZE;&lt;br /&gt;
&lt;br /&gt;
vs.&lt;br /&gt;
&lt;br /&gt;
function void uvm_packer::pack_field_int(logic [63:0] value, int size);&lt;br /&gt;
  for (int i=0; i&lt;size; i++)&lt;br /&gt;
    if(big_endian == 1)&lt;br /&gt;
      m_bits[count+i] = value[size-1-i];&lt;br /&gt;
    else&lt;br /&gt;
      m_bits[count+i] = value[i];&lt;br /&gt;
  count += size;&lt;br /&gt;
endfunction</description>
<guid>http://www.verilog.org/svdb/view.php?id=4031</guid>
<author>Janick Bergeron &lt;Janick Bergeron@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=4031#bugnotes</comments>
</item>
<item>
<title>0004030: `uvm_*pack_* macros lack begin/end</title>
<link>http://www.verilog.org/svdb/view.php?id=4030</link>
<description>The implementation of the `uvm*pack_* macros are multi-lines but are not enclosed within a begin/end block, preventing the macro from being treated as a single statement.</description>
<guid>http://www.verilog.org/svdb/view.php?id=4030</guid>
<author>Janick Bergeron &lt;Janick Bergeron@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=4030#bugnotes</comments>
</item>
<item>
<title>0003707: Clarify how the default driver/receiver supplies of primary inputs/ouputs are determined</title>
<link>http://www.verilog.org/svdb/view.php?id=3707</link>
<description>The attributes of driver_supply/receiver_supply of primary input/output ports determines the isolation/level shifter strategy which involves nets connected to those ports. User can specify the two attributes using set_port_attributes however a default definition will be handy.&lt;br /&gt;
&lt;br /&gt;
It is reasonable to assume the default driver_supply of primary input ports and default receiver_supply of the primary output ports is the primary supply set of the default power domain of current scope, i.e. domain created with -include_scope</description>
<guid>http://www.verilog.org/svdb/view.php?id=3707</guid>
<author>Qi Wang &lt;Qi Wang@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3707#bugnotes</comments>
</item>
<item>
<title>0003415: Check the example and decide whether SLEEP_MODE should involve reverse bias rather than forward bias - fix</title>
<link>http://www.verilog.org/svdb/view.php?id=3415</link>
<description>A very minor point, but I think the SLEEP_MODE in the example on page 47 should be reverse bias (nwell&gt;power) and not forward bias (power&gt;nwell) as shown:&lt;br /&gt;
&lt;br /&gt;
  -state SLEEP_MODE {–logic_expr {SW_ON &amp;&amp; interval(clk_dyn posedge negedge) &gt;= 100ns}&lt;br /&gt;
  -supply_expr {{power == ‘{FULL_ON, 0.8}}&lt;br /&gt;
  &amp;&amp; {ground == ‘{FULL_ON, 0}}&lt;br /&gt;
  &amp;&amp; {nwell == ‘{FULL_ON,0.6}}}&lt;br /&gt;
  –simstate CORRUPT_STATE_ON_CHANGE}</description>
<guid>http://www.verilog.org/svdb/view.php?id=3415</guid>
<author>John Biggs &lt;John Biggs@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3415#bugnotes</comments>
</item>
<item>
<title>0003320: Clarification on the instantiation hierarchy for '-location sibling' in set_isolation/level_shifter, see also 3194</title>
<link>http://www.verilog.org/svdb/view.php?id=3320</link>
<description>Whilst the other values of 'location' define where in the hierarchy (domain or logical?) the cells should be inserted the value 'sibling' does not seem to.&lt;br /&gt;
&lt;br /&gt;
&quot;sibling—a new sibling is created into which the isolation cells are placed.&quot;&lt;br /&gt;
&lt;br /&gt;
1. This infers that new hierarchy is created to store the cells of this strategy but where should this reside? Should we assume the location for this new hierarchy is derived from automatic location or something else?&lt;br /&gt;
&lt;br /&gt;
2. This probably depends on the answer to #1 but is one sibling used per strategy or per domain?&lt;br /&gt;
&lt;br /&gt;
3. Should 'sibling' be entered in 3.1 Definitions?&lt;br /&gt;
&lt;br /&gt;
Location sibling is also used in 6.41 and 6.42.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3320</guid>
<author>Gary_Delp &lt;Gary_Delp@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3320#bugnotes</comments>
</item>
<item>
<title>0003194: AKA 3194a: Clarification on the term 'sibling' when used to define location. (see 3320 for #1)</title>
<link>http://www.verilog.org/svdb/view.php?id=3194</link>
<description>Whilst the other values of 'location' define where in the hierarchy (domain or logical?) the cells should be inserted the value 'sibling' does not seem to.&lt;br /&gt;
&lt;br /&gt;
&quot;sibling—a new sibling is created into which the isolation cells are placed.&quot;&lt;br /&gt;
&lt;br /&gt;
1. This infers that new hierarchy is created to store the cells of this strategy but where should this reside? Should we assume the location for this new hierarchy is derived from automatic location or something else?&lt;br /&gt;
&lt;br /&gt;
2. This probably depends on the answer to #1 but is one sibling used per strategy or per domain?&lt;br /&gt;
&lt;br /&gt;
3. Should 'sibling' be entered in 3.1 Definitions?&lt;br /&gt;
&lt;br /&gt;
Location sibling is also used in 6.41 and 6.42.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3194</guid>
<author>Jon Worthington &lt;Jon Worthington@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3194#bugnotes</comments>
</item>
<item>
<title>0003043: Review and revise Clause 3 Definitions as required.</title>
<link>http://www.verilog.org/svdb/view.php?id=3043</link>
<description>The definition of driver (3.1.12) is “any design element that supplies a value to a net, either directly, or indirectly via a port.  Ports are not drivers.”  However, this doesn’t correlate well with the statement in 4.1 that says “A net that is not driven by design elements in a particular domain is not corrupted by that domain; input ports and assignment statements are not considered drivers in this context.”  This statement is intended to support the semantics of always-on signals that pass through a switched domain.  Unfortunately, the definition of driver in 3.1.12 restricts the effect of this statement to work only for pass through signals that originate in a parent context.  It does not appear to work for pass through signals that originate in a nested context. &lt;br /&gt;
&lt;br /&gt;
Suppose module instance A contains instance B which contains instance C, and each of A, B, C are in a separate power domain.  Suppose B is switched, and A and C are always on.  The current definition allows a signal from A to pass through B  on its way to C and remain uncorrupted.  That signal passes through an input port of B and an input port of C, neither of which is a driver, and therefore the signal is not corrupted.  But a signal coming from C passing through B on its way to A will be corrupted, because it must go through an output port of B, and output ports are considered drivers, so when the domain of B goes down, the signal entering A will be corrupted.  &lt;br /&gt;
&lt;br /&gt;
Perhaps the definition of a driver should be changed to read as follows:&lt;br /&gt;
&lt;br /&gt;
3.1.12 driver: Any logic that supplies a computed value to a net or port, or conditionally supplies a value to a net or port.  Ports themselves are not drivers, nor are Verilog continuous assignment statements or VHDL unconditional concurrent signal assignment statements that simply pass an input value to an output net, port, or signal, with no computation involved.”&lt;br /&gt;
&lt;br /&gt;
This proposed definition refers to &quot;computed&quot; values or &quot;conditional&quot; assignment because these imply combinational or sequential logic, whereas unconditional, continuous assignments do not.&lt;br /&gt;
&lt;br /&gt;
This definition should also state whether a Verilog buf primitive is considered to be a driver.  I believe all other primitives should be considered drivers.</description>
<guid>http://www.verilog.org/svdb/view.php?id=3043</guid>
<author>Erich Marschner &lt;Erich Marschner@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3043#bugnotes</comments>
</item>
<item>
<title>0003042: Clarify whether Verilog primitives create drivers</title>
<link>http://www.verilog.org/svdb/view.php?id=3042</link>
<description>The definition of design element (3.1.10) mentions (System)Verilog module instances, VHDL entity instances, and library cells.  There is no mention of Verilog primitives.  Should a Verilog primitive be considered a design element?  I.e., is it possible to specify that a Verilog primitive instance belongs to a given power domain?</description>
<guid>http://www.verilog.org/svdb/view.php?id=3042</guid>
<author>Erich Marschner &lt;Erich Marschner@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3042#bugnotes</comments>
</item>
<item>
<title>0003040: Revise add_power_state syntax to conform to UPF conventions</title>
<link>http://www.verilog.org/svdb/view.php?id=3040</link>
<description>The add_power_state is defined as:&lt;br /&gt;
add_power_state object_name&lt;br /&gt;
                                {-state state_name {[-supply_expr {boolean_function}] [-logic_expr {boolean_function}]&lt;br /&gt;
                                [-simstate simstate] [-legal | -illegal] [-update]}}*&lt;br /&gt;
                                [-simstate simstate][-legal | -illegal]&lt;br /&gt;
                                [-update]&lt;br /&gt;
&lt;br /&gt;
According to section 6.1, All parameters begin with a hyphen (-)....&quot;. So -state defines a parameter. According to Tcl syntax, a parameter has three basic data types:&lt;br /&gt;
&lt;br /&gt;
a.	Scalar (or string)&lt;br /&gt;
b.	List (an ordered list of scalars)&lt;br /&gt;
c.	Array (or hash)&lt;br /&gt;
&lt;br /&gt;
The current syntax is not compliant with the Tcl syntax!&lt;br /&gt;
&lt;br /&gt;
I suggest to correct the command syntax as:&lt;br /&gt;
&lt;br /&gt;
add_power_state object_name&lt;br /&gt;
                                {-state {state_name [-supply_expr {boolean_function}] [-logic_expr {boolean_function}]&lt;br /&gt;
                                [-simstate simstate] [-legal | -illegal] [-update]}}*&lt;br /&gt;
                                [-simstate simstate][-legal | -illegal]&lt;br /&gt;
                                [-update]&lt;br /&gt;
&lt;br /&gt;
This correction is consistent with Tcl syntax and similar to add_port_state command:&lt;br /&gt;
&lt;br /&gt;
add_port_state port_name {-state {name &lt;nom | min max | min nom max | off&gt;}}*</description>
<guid>http://www.verilog.org/svdb/view.php?id=3040</guid>
<author>Shir-Shen Chang &lt;Shir-Shen Chang@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=3040#bugnotes</comments>
</item>
<item>
<title>0002966: Check that use of {} is self-consistent and consistent with tcl and revise as needed.</title>
<link>http://www.verilog.org/svdb/view.php?id=2966</link>
<description>Please notate changes needed.</description>
<guid>http://www.verilog.org/svdb/view.php?id=2966</guid>
<author>Gary_Delp &lt;Gary_Delp@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=2966#bugnotes</comments>
</item>
<item>
<title>0002965: Clarify that add_power_state requires an empty set of braces in certain cases (cf 3040)</title>
<link>http://www.verilog.org/svdb/view.php?id=2965</link>
<description>add_power_state PdA.primary&lt;br /&gt;
-state GO_MODE {–logic_expr SW_ON –simstate NORMAL&lt;br /&gt;
-supply_expr {{power == ‘{FULL_ON, 0.8}}&lt;br /&gt;
&amp;&amp; {ground == ‘{FULL_ON, 0}}&lt;br /&gt;
&amp;&amp; {nwell == ‘{FULL_ON,0.8}}}&lt;br /&gt;
-state OFF_MODE {–logic_expr !SW_ON&lt;br /&gt;
-supply_expr {power == ‘{OFF}}&lt;br /&gt;
–simstate CORRUPT}&lt;br /&gt;
-state OVERVOLTAGE_MODE {–logic_expr !SW_ON&lt;br /&gt;
-supply_expr {power == ‘{FULL_ON, 1.3 5.0}}&lt;br /&gt;
–simstate CORRUPT&lt;br /&gt;
-illegal }&lt;br /&gt;
	-state {ILLUSTRATION1}&lt;br /&gt;
	-state ILLUSTRATION2 {} # {} is Currently required&lt;br /&gt;
	-state ILLUSTRATION3&lt;br /&gt;
	&lt;br /&gt;
-state SLEEP_MODE {&lt;br /&gt;
–logic_expr &lt;br /&gt;
{SW_ON &lt;br /&gt;
&amp;&amp; interval(clk_dyn posedge negedge)&gt;= 100ns}&lt;br /&gt;
-supply_expr {{power == ‘{FULL_ON, 0.8}}&lt;br /&gt;
&amp;&amp; {ground == ‘{FULL_ON, 0}}&lt;br /&gt;
&amp;&amp; {nwell == ‘{FULL_ON,0.6}}}&lt;br /&gt;
–simstate CORRUPT_STATE_ON_CHANGE}&lt;br /&gt;
-legal</description>
<guid>http://www.verilog.org/svdb/view.php?id=2965</guid>
<author>Gary_Delp &lt;Gary_Delp@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=2965#bugnotes</comments>
</item>
<item>
<title>0002868: FAQ: Clarify whether -transitive is allowed with no value</title>
<link>http://www.verilog.org/svdb/view.php?id=2868</link>
<description>The syntax example in 7.1 (find_objects) is:&lt;br /&gt;
&lt;br /&gt;
find_objects ... -transitive.&lt;br /&gt;
&lt;br /&gt;
The syntax specification specifies that the -transitive should take the values TRUE | FALSE.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
This occurs elsewhere throughout the syntax examples in the spec, e.g. section 7.18.</description>
<guid>http://www.verilog.org/svdb/view.php?id=2868</guid>
<author>Jon Worthington &lt;Jon Worthington@example.com&gt;</author>
<comments>http://www.verilog.org/svdb/view.php?id=2868#bugnotes</comments>
</item>
</channel>
</rss>

