//----------------------------------------------------------------------
// This File: clk0test.v
//
// Sunburst Design (Beaverton, OR): 
//            cliffc@sunburst-design.com
//            www.sunburst-design.com
//----------------------------------------------------------------------
`define CYCLE 10
`timescale 1ns / 1ns
module clk0test;
  logic clk, rst_n;

  //-------------------------------------------------------------------
  // Clock oscillator
  //-------------------------------------------------------------------
  initial begin
    clk <= 0;
    forever #(`CYCLE/2) clk = ~clk;
  end

  //-------------------------------------------------------------------
  // First negedge clk at time 0
  //-------------------------------------------------------------------
  default clocking cb0 @(negedge clk);
  endclocking

  //-------------------------------------------------------------------
  // Test code 
  //-------------------------------------------------------------------
  initial begin
    init_reset;
    ##6;
    reset;
    ##4;
    reset(3);
    ##3 $finish;
  end

  //-------------------------------------------------------------------
  // Reset commands: init_reset (time-0 reset) & reset
  //-------------------------------------------------------------------
  task init_reset;
    `ifdef NODLY
        rst_n <= '0; // +define+NODLY
    `else
    ##1 rst_n <= '0; // Should this happen at time-0 or time-10?
    `endif
    ##1 rst_n  = '1;
  endtask
  
  task reset (input int cnt=1);
    ##1 rst_n  = '0;
    repeat(cnt) ##1;
        rst_n  = '1;
  endtask

  initial begin
    $timeformat(-9,0,"ns",6);
    $monitor("%t: rst_n=%b", $time, rst_n);
  end
endmodule