0002971: allow scope constraint definiton (in module/interface/program/checker)

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Category

Severity

Date Submitted

Last Update

0002971

[SystemVerilog P1800] SV-EC

feature

2010-02-03 07:28

2010-02-08 15:44

Reporter

Mirek Forczek

View Status

public

Assigned To

Priority

normal

Resolution

open

Status

new

Product Version

1800-2009

Summary

0002971: allow scope constraint definiton (in module/interface/program/checker)

Description

allow constraint declaration at module/interface/program/checker unrelated to any class, intended for use with std::randomize().

Additional Information

(
    example, depends on:
        - (0002968) allow constraint reference at constraint expression
)

module M;
    int x;
    int y;

        constraint c1 { x<y; }
        constraint c2 { x>10; }
        constraint c3 { y<30; }

    initial
        std::randomize(x,y) with { c2 && (c1 || c3); };
endmodule

Tags

No tags attached.

Type

Enhancement

Attached Files

Relationships

child of

0003144

new

Master issue for SV-EC Constrained random value generation issues

There are no notes attached to this issue.

Issue History
Date Modified	Username	Field	Change
2010-02-03 07:28	Mirek Forczek	New Issue
2010-02-03 07:28	Mirek Forczek	Type	=> Errata
2010-02-04 00:54	shalom	Issue Monitored: shalom
2010-02-08 15:44	mehdi_mohtashemi	Type	Errata => Enhancement
2010-07-12 06:01	shalom	Relationship added	child of 0003144

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