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| ID | Category | Severity | Date Submitted | Last Update | |||
| 0002370 | [SystemVerilog P1800] SV-SC | minor | 2008-04-25 18:17 | 2008-08-18 18:19 | |||
| Reporter | Neil Korpusik | View Status | public | ||||
| Assigned To | |||||||
| Priority | normal | Resolution | duplicate | ||||
| Status | closed | Product Version | P1800-2008/D4 | ||||
| Summary | 0002370: Inferred clock ambiguities with the sampled functions - Champions feedback on 1698 | ||||||
| Description |
This is Champions feedback on 0001698. The proposal for 0001698 seems to have an issue with assertions in procedural code. There seems to be something missing on how putting $past into the procedural code is meant to work. This needs to be reviewed with the sv-sc. The rules for clock inferencing are appear to be incomplete. $past() without specifying the cycle it is sampled on is something new. Some didn't see how it can always be inferring sampled points. The "sampled functions" are still not fully defined. It isn't clear when things will be sampled. The goal is for all simulators to use the same rules. Other Comments: Some people don't like seeing contexts of $rose, etc. in conjunction with always_ff. This isn't meant to be synthesizable code. It isn't illegal but some people don't like that coding style. It isn't synthesizable sequential logic. It isn't sequential logic that accurately represents logic behavior. |
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| Tags | No tags attached. | ||||||
| Type | Errata | ||||||
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