Unassigned [^] (1 - 10 / 1011) 0004170   Cleanup: examples in section 6.6.1 [VerilogAMS] Conflict - 2012-05-21 12:06 0004169   m_top_all_dropped need to be cleared on raising objection to prevent simulation for being terminated too early [VIP] BCL - 2012-05-21 04:47 0004168   bit bash ignores uvm_reg_map::add_reg(.rights()) [VIP] Registers - 2012-05-21 00:36 0004167 Syntax 25-3 needn't excerpt footnote 9, because footnote should be on first production in A.2.1.3 [SystemVerilog P1800] SV-EC - 2012-05-19 18:30 0004166   Augment the error message when cloning a component to identify the component attempting to be cloned. [VIP] BCL - 2012-05-19 06:13 0004165   document and implementation is inconsistent regarding the report server singleton [VIP] BCL - 2012-05-17 22:12 0003568   `uvm_do_obj_callbacks_exit_on has return statements [VIP] BCL - 2012-05-17 11:39 0003645 Apply consistent Report ID convention [VIP] BCL - 2012-05-17 11:38 0003651 Formalize accept/begin/end_tr use model for sequencer/driver sync [VIP] BCL - 2012-05-17 11:38 0003662   packing of strings using NULL termination not compatible with bitstream ops [VIP] BCL - 2012-05-17 11:37	Resolved [^] (1 - 10 / 14) 0004049 Incompatible syntax of -source/-sink compared to set_isolation [Power Aware P1801] 6.42 set_level_shifter - 2012-04-06 11:37 0004028 -applies_to and -source/-sink illegal? [Power Aware P1801] 6.40 set_isolation - 2012-04-04 10:27 0004000 Clarify if legality of predefined states (DEFAULT_NORMAL, DEFAULT_CORRUPT) of a supply set can be changed or not [Power Aware P1801] 5.04.2 Power states of supply sets - 2012-04-04 10:27 0003944 Possible typo and contradictory statements w.r.t. undefined states of supply set [Power Aware P1801] 5.04.2 Power states of supply sets - 2012-04-04 10:27 0003916 Clarify how -models affect the effective_element_list semantics when specified along with -elements/exclude_elements [Power Aware P1801] 6.03 effective_element_list semantics - 2012-04-04 10:27 0003818   Add -elements and -exclude_elements to set_simstate_behavior [Power Aware P1801] 6.51 set_simstate_behavior - 2012-04-04 10:27 0003771   AKA 3771a: Define an object-oriented (syntactically bounded) approach for modeling IP block power aspects [Power Aware P1801] Additional Capabilties - 2012-04-04 10:27 0003546 AKA 3546a: Change filter options on set_iso/ls to apply to explicit ports in -elements (filtering may trigger warning) [Power Aware P1801] 6.42 set_level_shifter - 2012-04-04 10:27 0002852 Clarify whether NOT_NORMAL is one of the enumerated simstates that can be returned by functions (fixed - NOT) [Power Aware P1801] 5.04.3 Power states of power domains - 2012-04-04 10:27 0004083 Contradictory statement for VCT [Power Aware P1801] 6.16 create_hdl2upf_vct - 2012-04-04 10:20
Recently Modified [^] (1 - 10 / 4115) 0004170   Cleanup: examples in section 6.6.1 [VerilogAMS] Conflict - 2012-05-21 12:06 0004140   uvm_reg_hw_reset_seq attempts to read Write-Only registers [VIP] Registers - 2012-05-21 11:39 0003879   2012 Ballot comment 40: Return value of sequence methods should be well-defined [SystemVerilog P1800] SV-AC - 2012-05-21 10:42 0003127 2012 Ballot comment 57: cbStartOfReset and cbEndOfReset callbacks are not documented [SystemVerilog P1800] SV-CC - 2012-05-21 10:38 0004129   2012 Ballot comment 50: Need to clarify ambiguous binding of matches operator [SystemVerilog P1800] SV-EC - 2012-05-21 10:15 0004128   2012 Ballot comment 49: Global constants should be allowed as variables in a covergroup_expression [SystemVerilog P1800] SV-EC - 2012-05-21 10:15 0004127   2012 Ballot comments 23, 48: difference between BNF and example whether data_type appears before or after cover_point_identifier [SystemVerilog P1800] SV-EC - 2012-05-21 10:12 0004076   2012 Ballot comments 19, 20, 39: Inconsistency in description of sequence methods [SystemVerilog P1800] SV-AC - 2012-05-21 10:10 0004045   2012 Ballot comment 43: checker_declaration BNF does not allow nested checker declaration [SystemVerilog P1800] SV-AC - 2012-05-21 10:09 0003982   2012 Ballot comment 36: clocking_decl_assign allows expression or just hierachical_identifier [SystemVerilog P1800] SV-EC - 2012-05-21 10:08
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