Electronic Design Process Subcommittee of IEEE DATC

Online Record of the
EDP 2005 Workshop

Prior Years: 2004 2003 2002 2001 2000

which took place
April 7,8, 2005 in Monterey California

Organized in cooperation with ISPD (www.ispd.cc)

Presentations and Papers from EDPS 2005

Other Slides and Papers from EDPS 2005

Scenes from EDPS2005

John Darringer	IBM	System level design and flows for big chips
Greg Spirakis		Designing for 65nm and Beyond which refers to Alberto SV's DAC talk Benefits and Challenges for Platform-Based Design
Gadi Singer	Intel	Design at Large: Emergence of Platform Oriented Design (Slides not yet available)

General Chair	Dwight Hill (Synopsys)
Program Chair	John Lillis (U of Ill)
Proceedings Chair	Aparna Dey (Cadence)
Publicity Chair	Bhanu Kapoor (Atrenta)

The Electronic Design Processes (EDP) Workshop provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. As the requirements and complexities of electronic design increase, past ad hoc approaches to design processes are proving inadequate. The workshop focuses on the facilitation and improvement of the overall design process, rather than on the functions of the individual tools themselves. Topics include interactions among and between tools and designers, the infrastructures supporting these interactions, and the frameworks in which these interactions take place.

Partial list of Speakers:

Speaker Topic

John M Acken Oklahoma State John Acken A
Methodology to Decrease Product Development time While increasing Product Quality

Laurence Brevard Synopsys
Milkyway for Large Designers

Juan-Antonio Caballa IBM Juan-Antonio Carballo
Open hardware, open design software, and the VC ecosystem dilemma

John Darringer (keynote) IBM
System level design and flows for big chips

Saverio Fazzari Cadence
The impact of reuse requirements on IP

Wolfgang Fichtner Silicon Eng./Synopsys Wolfgang Fitchner
Closing the Gap Between Manufacturing and Design

Patrick Groeneveld Magma
Engineering a Comprehensive EDA Datamodel from from Scratch

Yu-Chin Hsu Novas
Debugging Silicon Prototypes

Haiming Jin Intel

Design and Test of a Mixed-Signal Application-Specific Video Encoder

Andrew Kahng Blaze/UCSD

On Transparency in Design for Manufacturing

Eric Leavitt Cadence
Open Access Data Model

Patrick Madden SUNY Binghamton
Supersize VLSI, A Recipe for Disaster

Igor Markov U Mich
Tool Development Infrastructure for Multi-Million Gate Designs

Joydeep Mitra Magma
RADAR- RET-Aware Detailed Routing

David Pan U Texas
Diffusion-based Placement Migration

Sachin Sapatnekar & Nagib Hakim U Minn/ Intel
Statistically-based design automation for timing and power

Gadi Singer (Friday keynote)

Intel Gadi Singer

Greg Spirakis (dinner keynote) Designing for 65nm and Beyond

Joe Shinnerl UCLA
Large Scale Circuit Placement: Gap and Progress

David Thon Cadence
Using Yield-Focused Design Methodologies
to Speed Time-to-Market

Andres Torres Mentor
Towards Manufacturability Closure: Process Variations and Layout Design

Session Schedule

Wednesday, April 6th
Reception and Registration (5pm to 7:30pm)		Captain's Table, 4th floor


Thursday, April 7th, Point Cabrillo

Breakfast (8am to 9am)


Welcome
Dwight Hill	Synopsys

Keynote (9:05)
John Darringer	IBM	System level design and flows for big chips


Break (10:05 am)

Placement and Floorplanning (10:30)		John Lillis (Chair)
Joe Shinnerl (co-author w/ J. Cong)	UCLA	Large Scale Circuit Placement: Gap and Progress
David Pan	U Texas	Diffusion-based Placement Migration
Yu-Chin Hsu	Novas	Debugging Silicon Prototypes

Thurs Lunch (Point Alones) (noon to 1pm)


Enabling Technologies for SS Design (1pm)		Bhanu Kapoor (Chair)
Ashwin K.Kumaraswamy	UK	System on Chip Design Framework
Saverio Fazzari	Cadence	The impact of reuse requirements on IP
Nagib Hakim	Intel	Title: Statistically-based design automation for timing and power
Sachin Sapatnekar	U Minn	(second half of timing talk)

Break (3pm)

DFM Issues and Answers (3:30)		Takahide Inoue (chair)
Andrew Kahng	Blaze/UCSD	On Transparency in Design for Manufacturing
Andres Torres	Mentor	Towards Manufacturability Closure: Process Variations and Layout Design
Rajit Chandra	Gradient	The impact of thermal analysis on large chip design
Juan-Antonio Carballo	IBM	Open hardware, open design software, and the VC ecosystem dilemma



End of day (5:30 pm), drive to Dinner at 7pm)

Dinner (7pm)
Dinner Keynote (approx 8:30)		Gary Smith (hosting)
Greg Spirakis (dinner keynote)		Designing for 65nm and Beyond

(drive back to Monterey Beach Hotel)



Friday, April 8th (meetings move to Point Pinos)

Breakfast (7:30 to 8:30)

Keynote (8:30 am)		Dwight Hill (host)
Gadi Singer	Intel	Title TBD


Forward Looking Silicon Technologies (9:30)
Wolfgang Fichtner	Synopsys	DFM and ITRS for large scale


Break (10:00)

Big Issues in Big Chips (10:30 am)		TBD (chair)
Jurjen Westra	Einhdoven	Global Routing: Metrics, Benchmarks, and Tools
Joydeep Mitra	U Texas/Magma	RADAR- RET-Aware Detailed Routing
David Thon	Cadence	Using Yield-Focused Design Methodologies to Speed Time-to-Market
Haiming Jin	Intel	Design and Test of a Mixed-Signal Application-Specific Video Encoder



Friday Lunch (Point Alones) (12:30 pm to 1:30)

SuperSize Flows (1:30 pm)		Jos� Lima (chair)
Igor Markov	U of Mich	Tool Development Infrastructure for Multi-Million Gate Designs
John Acken	Oklahoma	A Methodology to Decrease Product Development time While increasing Product Quality
Patrick Madden	SUNY Binghamton	Supersize VLSI, A Receipt for Disaster



Break (3:00)

Databases and Infrastructure (3:30)		Aparna Dey (chair)
Patrick Groeneveld	Magma	Engineering a comprehensive EDA datamodel from scratch
Eric Leavitt	Cadence	Open Access Data Model
Laurence Brevard	Synopsys	Milkyway for large designs

Closing 5:00 pm

Technical Program Committee

(in alphabetic order)

Juan-Antonio Carballo (IBM)	Aparna Dey (Cadence)	Steve Grout
Dwight Hill (Synopsys)	Takahide Inoue (STARC)	Bhanu Kapoor (Atrenta)
John Lillis (U of Ill)	Andrew Kahng (UCSD)	José Augusto Lima ( Univ. of Minho)
Gabe Moretti (EDN)	Greg Peterson (U. of Tennessee)	Naresh Sehgal (Intel)
Gary Smith (Gartner/Dataquest)

General Information on EDPS:

The Electronic Design Process Subcommittee (EDPS) is a technical subcommittee of the IEEE Computer Society's Design Automation Technical Committee (DATC).

Objectives of the EDPS:

The EDPS focuses on design process for electronics products with respect to design, design technology, and design productivity for both today's and coming technologies.

Activities and Achievements:

To provide a forum for electronics designers and CAD/EDA technologists to work together on design process issues, the EDPS holds an annual workshop to discuss design and EDA process problems, plans, and research.

In addition, the EDPS often holds a Birds of a Feather (BOF) at annual Design Automation Conferences (DAC), and also meets at ICCAD. Contact the EDPS Steering Committee for details.

Past EDPS Activities:

	The 2004 EDP Workshop: main page (includes pointers to papers)
	The 2003 EDP Workshop: main page (includes pointers to papers)
	The 2002 EDP Workshop: main page (includes pointers to papers)
	The 2001 EDP Workshop: main page (includes pointers to papers)
	The 2000 EDP workshop: technical program and presentations and call for papers.
	The agenda for the mini-EDP workshop that was held at ICCAD 1999.
	The 1999 EDP workshop: call for papers.
	The 1997 EDP workshop.

Electronic Design Process Email List:

The email list for general information and announcements on EDPS is edps-all@eda.org.
To join the email list for the IEEE DATC EDPS group, send a request to the sysop below.

EDPS Co-chairs:

Dwight Hill and Naresh Sehgal

www.eda.org/edps Group Sysop:

Steve Grout

About the eda.org machine

There are many groups with repositories and email exploders on the VHDL International Users' Forum (VIUF) Internet Services (VIIS) System. For more information about the VIIS supported features and access mechanisms (such as email, Internet or public dial-up), click here.

Last updated Nov 5, 2004 by Dwight_Hill